Presentation | 2014-11-06 Modeling and Simulation of Charge-Trapping Memory and Reliability Issues Takamitsu ISHIHARA, Naoki YASUDA, Shosuke FUJII, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Charge-trapping memory is one of the most promising candidates as the next generation memory. The complicated operation mechanism requires modeling and simulation on the basis of the experiment for the systematic understanding of the operation. Write/erase and data retention characteristics are well understood by the modeling and TCAD simulation. Reliability issues are left to be focused on by modeling and simulation. As perspective, experimental results related with the reliability are presented. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Charge-Trapping Memory / Write/Erase characteristics / Modeling / Measurement / Reliability |
Paper # | SDM2014-102 |
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Committee | SDM |
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Conference Date | 2014/10/30(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Silicon Device and Materials (SDM) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Modeling and Simulation of Charge-Trapping Memory and Reliability Issues |
Sub Title (in English) | |
Keyword(1) | Charge-Trapping Memory |
Keyword(2) | Write/Erase characteristics |
Keyword(3) | Modeling |
Keyword(4) | Measurement |
Keyword(5) | Reliability |
1st Author's Name | Takamitsu ISHIHARA |
1st Author's Affiliation | Advanced LSI Technology Laboratory, Toshiba() |
2nd Author's Name | Naoki YASUDA |
2nd Author's Affiliation | Semiconductor & Storage Company, Toshiba |
3rd Author's Name | Shosuke FUJII |
3rd Author's Affiliation | Advanced LSI Technology Laboratory, Toshiba |
Date | 2014-11-06 |
Paper # | SDM2014-102 |
Volume (vol) | vol.114 |
Number (no) | 291 |
Page | pp.pp.- |
#Pages | 6 |
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