Presentation	2014-11-26 Time Analysis of Appling Back Gate Bias for Reconfigurable Architectures Hayate OKUHARA, Hideharu AMANO,
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Abstract(in English)	The response time of the dynamic back gate bias scaling of large scale digital modules implemented with silicon on thin BOX (SOTB) technology developed by LEAP was analyzed using real chips. A reconfigurable accelerator cool mega array (CMA) and two different prototypes of microcontroller V850 E-star were utilized for measurement. Evaluation results revealed that the response time is related to the chip area which shares the bias voltage rather than the leakage current itself. The leakage current can be mostly stable after 180.0us and 270.2us after changing bias voltage of CMA and V850E-Star, respectively. The possibility of the dynamic back gate bias scaling within milliseconds for dynamic reconfigurable architectures was shown.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Dynamic back gate bias scaling / Low power design
Paper #	RECONF2014-36
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Committee	RECONF
Conference Date	2014/11/19(1days)
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Paper Information
Registration To	Reconfigurable Systems (RECONF)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Time Analysis of Appling Back Gate Bias for Reconfigurable Architectures
Sub Title (in English)
Keyword(1)	Dynamic back gate bias scaling
Keyword(2)	Low power design
1st Author's Name	Hayate OKUHARA
1st Author's Affiliation	Faculty of science and Technology Keio University()
2nd Author's Name	Hideharu AMANO
2nd Author's Affiliation	Faculty of science and Technology Keio University
Date	2014-11-26
Paper #	RECONF2014-36
Volume (vol)	vol.114
Number (no)	331
Page	pp.pp.-
#Pages	6
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