| Presentation | 2014-11-28 On-chip delay measurement for FPGAs Kentaro ABE, Yousuke MIYAKE, Seiji KAJIHARA, Yasuo SATO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes an on-chip delay measurement method that targets a logic circuit on an FPGA. While advances in semiconductor technology bring miniaturization and performance improvement of the circuit, failures due to the delay degradation by aging after shipment have become a crucial problem. When a logic circuit is configured on an FPGA, the number of transistors to be used for the circuit increases compared to cases of LSIs such as ASICs. Therefore, if the FPGA is used for a long time, the circuit will not operate correctly due to the aging of the transistors, and such a concern for the FPGA will be more serious than that of LSI. To conquer this problem, a method of measuring a circuit delay with variable test timing generated by a PLL's phase shift function has been proposed. In this work, the variable test timing generator is implemented on the FPGA, and an on-chip delay measurement is performed. Then, we describe a method to measure the delay margin of the circuit varying the test-timing. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Built-in Self-Test / delay measurement / variable test-timing |
| Paper # | VLD2014-109,DC2014-63 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2014/11/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On-chip delay measurement for FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Built-in Self-Test |
| Keyword(3) | delay measurement |
| Keyword(4) | variable test-timing |
| 1st Author's Name | Kentaro ABE |
| 1st Author's Affiliation | Kyushu Institute of Technology() |
| 2nd Author's Name | Yousuke MIYAKE |
| 2nd Author's Affiliation | Kyushu Institute of Technology |
| 3rd Author's Name | Seiji KAJIHARA |
| 3rd Author's Affiliation | Kyushu Institute of Technology |
| 4th Author's Name | Yasuo SATO |
| 4th Author's Affiliation | Kyushu Institute of Technology |
| Date | 2014-11-28 |
| Paper # | VLD2014-109,DC2014-63 |
| Volume (vol) | vol.114 |
| Number (no) | 329 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |