| Presentation | 2014-11-28 A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS Yasufumi Sakai, Takayuki Shibasaki, Takumi Danjo, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | To meet ever-increasing demands for computing power in data centers, data rates over 50Gbps/signal (e.g., OIF CEI-56G-VSR) will eventually be required in wireline chip-to-chip communications within and between servers. This paper shows a 56-Gb/s receiver front-end suited for baud-rate clock recovery. Sharing the comparators for the data decision and phase detection minimizes the number of comparators in the front-end and reduces the power consumption. The front-end has a continuous-time linear equalizer followed by a 1-tap speculative decision-feedback equalizer. The front-end operates at 56Gb/s with a bit error rate of less than 10^<-12> with a 0.4UI margin in the bathtub curve. It occupies 0.27mm^2 and consumes 177mW of power from a 0.9-V supply. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CMOS / High-Speed I/O / Phase Detector / Decision Feedback Equalizer / Comparator |
| Paper # | VLD2014-96,CPM2014-127,ICD2014-70,CPSY2014-84,DC2014-50,RECONF2014-45 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2014/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS |
| Sub Title (in English) | |
| Keyword(1) | CMOS |
| Keyword(2) | High-Speed I/O |
| Keyword(3) | Phase Detector |
| Keyword(4) | Decision Feedback Equalizer |
| Keyword(5) | Comparator |
| 1st Author's Name | Yasufumi Sakai |
| 1st Author's Affiliation | Fujitsu Laboratories Ltd.() |
| 2nd Author's Name | Takayuki Shibasaki |
| 2nd Author's Affiliation | Fujitsu Laboratories Ltd. |
| 3rd Author's Name | Takumi Danjo |
| 3rd Author's Affiliation | Fujitsu Laboratories Ltd. |
| 4th Author's Name | Hisakatsu Yamaguchi |
| 4th Author's Affiliation | Fujitsu Laboratories Ltd. |
| 5th Author's Name | Toshihiko Mori |
| 5th Author's Affiliation | Fujitsu Laboratories Ltd. |
| 6th Author's Name | Yoichi Koyanagi |
| 6th Author's Affiliation | Fujitsu Laboratories Ltd. |
| 7th Author's Name | Hirotaka Tamura |
| 7th Author's Affiliation | Fujitsu Laboratories Ltd. |
| Date | 2014-11-28 |
| Paper # | VLD2014-96,CPM2014-127,ICD2014-70,CPSY2014-84,DC2014-50,RECONF2014-45 |
| Volume (vol) | vol.114 |
| Number (no) | 332 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |