Presentation 2014-10-02
Study on Target Impedance of Power Supply Network for Maintain Power and Signal Integrity
Toma Yamaguchi, Tosio Sudo,
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Abstract(in English) Reduction of Power distribution networks (PDN) impedance is necessary to prevent poor operation of the chip. A way of thinking called target impedance is used as a method to set PDN impedance. However, target impedance did not change by frequency and was not considered about high frequency range. Therefore get Consumption electric current spectrum of the chip by analysis of the whole system which connected an equivalent circuit model of the power supply system of ASIC to and derive target impedance with Frequency properties. I derive E in this study by making the model who can analyze Power Integrity (PI) and Signal Integrity (SI) at the same time and inspect the validity.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Target impedance / PDN impedance / Anti-resonance peak / Power integrity / Signal integrity / Power supply noise
Paper # VLD2014-65,ICD2014-58,IE2014-44
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Conference Information
Committee VLD
Conference Date 2014/9/25(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Study on Target Impedance of Power Supply Network for Maintain Power and Signal Integrity
Sub Title (in English)
Keyword(1) Target impedance
Keyword(2) PDN impedance
Keyword(3) Anti-resonance peak
Keyword(4) Power integrity
Keyword(5) Signal integrity
Keyword(6) Power supply noise
1st Author's Name Toma Yamaguchi
1st Author's Affiliation Shibaura-Institute of Technology()
2nd Author's Name Tosio Sudo
2nd Author's Affiliation Shibaura-Institute of Technology
Date 2014-10-02
Paper # VLD2014-65,ICD2014-58,IE2014-44
Volume (vol) vol.114
Number (no) 231
Page pp.pp.-
#Pages 6
Date of Issue