| Presentation | 2014-10-10 Study of Processor Core for Many-core Architecture Combining ALU Cascading and 3-way In-order Execution Hajime SHIMADA, Ryotaro KOBAYASHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recent many-core processor frequently utilizes 2-way in-order execution core which is diverted from high-performance embedded processor core due to good area / energy efficiency. However, current high-performance embedded processor core aims to extend itselfto 2-way out-of-order execution for performance. But it requires additional circuit required for out-of-order execution so that it degrades area / energy efficiency. In this paper, we discuss area / energy efficient processor core which is derived from in-order execution extension. Generally, there's almost no effectiveness in 3-way in-order execution because the effectiveness is limited by data dependency. We consider to break this limitation by utilizing ALU cascading which executes several ALU arithmetic in one clock cycle. ALU cascading cannot apply around upper bound of operatable clock frequency, but current processor infrequently utilize upper bound of operatable clock frequency so that we thought there's enough application chance. To confirm effectiveness of the proposal, we compared processor performance among proposed 3-way in-order execution with ALU cascading and 2-way out-of-order execution under SPEC CPU 2000 integer benchmarks. We confirmed that the proposal gives better performance compared to 2-way out-of-order if the proposed core has 2 stage shorter pipeline due to in-order execution. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Processor architecture / Energy efficiency / Circuit area efficiency |
| Paper # | CPSY2014-53 |
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| Committee | CPSY |
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| Conference Date | 2014/10/3(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Study of Processor Core for Many-core Architecture Combining ALU Cascading and 3-way In-order Execution |
| Sub Title (in English) | |
| Keyword(1) | Processor architecture |
| Keyword(2) | Energy efficiency |
| Keyword(3) | Circuit area efficiency |
| 1st Author's Name | Hajime SHIMADA |
| 1st Author's Affiliation | Information Technology Center, Nagoya University() |
| 2nd Author's Name | Ryotaro KOBAYASHI |
| 2nd Author's Affiliation | Grad. Sch. of Engineering, Toyohashi University of Technology |
| Date | 2014-10-10 |
| Paper # | CPSY2014-53 |
| Volume (vol) | vol.114 |
| Number (no) | 242 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |