| Presentation | 2014-09-05 GPU implementation of Ciphers using Schematic to Program Translator (SPT) Masashi WATANABE, Keisuke IWAI, Hidema TANAKA, Takakazu KUROKAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With the spread of heterogeneous computing, accelerators such as GPU are widely used. However, it is not easy to develop a software program that runs at high speed on accelerators. On the other hand, encryption algorithms are evaluated with not only the strength but also the implementability and the performance. Therefore it is important to compare the performance by throughput using accelerators. We proposed a development tool named SPT(Schematic to Program Translator) for high-speed processing of encryption as well as FPGA and many-core processor. In this paper, we discussed GPU implementation of Cipher using SPT. In this tool, a C program is automatically generated from the figure drawn in accordance with the specifications of the encryption algorithm. Moreover, many-core processor, GPU and FPGA can be easily used by passing the program to the C compiler, CUBA translator and high-level synthesis tool. As a result, programs generated by CUBA transrator using C programs generated by SPT can perfprm encryption process correctly on GPU, however its performance became slower than codes generated by person. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | GUI / Implementation of Encryption Circuit / AES / Camellia / CUDA / GPU |
| Paper # | ISEC2014-52 |
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| Conference Information | |
| Committee | ISEC |
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| Conference Date | 2014/8/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Information Security (ISEC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | GPU implementation of Ciphers using Schematic to Program Translator (SPT) |
| Sub Title (in English) | |
| Keyword(1) | GUI |
| Keyword(2) | Implementation of Encryption Circuit |
| Keyword(3) | AES |
| Keyword(4) | Camellia |
| Keyword(5) | CUDA |
| Keyword(6) | GPU |
| 1st Author's Name | Masashi WATANABE |
| 1st Author's Affiliation | National Defense Academy of Japan() |
| 2nd Author's Name | Keisuke IWAI |
| 2nd Author's Affiliation | National Defense Academy of Japan |
| 3rd Author's Name | Hidema TANAKA |
| 3rd Author's Affiliation | National Defense Academy of Japan |
| 4th Author's Name | Takakazu KUROKAWA |
| 4th Author's Affiliation | National Defense Academy of Japan |
| Date | 2014-09-05 |
| Paper # | ISEC2014-52 |
| Volume (vol) | vol.114 |
| Number (no) | 203 |
| Page | pp.pp.- |
| #Pages | 8 |
| Date of Issue | |