| Presentation | 2014-09-19 FPGA Implementation of a Compact Processor Yukiyama for Tiny SoC Yuichi WATANABE, Kazuya TANIGAWA, Tetsuo HIRONAKA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a small soft-core processor architecture that can be napped to a CPLD. This paper describes the detail of the proposed soft-core processor architecture and its compiler as its software-development environment, and also presents an example how the soft-core processor, and its compiler are used for developing a simple SoC. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Tiny Processor / SoC / Soft-core-IP |
| Paper # | RECONF2014-31 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2014/9/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | FPGA Implementation of a Compact Processor Yukiyama for Tiny SoC |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Tiny Processor |
| Keyword(3) | SoC |
| Keyword(4) | Soft-core-IP |
| 1st Author's Name | Yuichi WATANABE |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Kazuya TANIGAWA |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| 3rd Author's Name | Tetsuo HIRONAKA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| Date | 2014-09-19 |
| Paper # | RECONF2014-31 |
| Volume (vol) | vol.114 |
| Number (no) | 223 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |