| Presentation | 2014-09-18 A Time-division Multiplexing Method of Inter-FPGA Signals for Multi-FPGA Systems with Various Topologies Masato INAGI, Yuichi NAKAMURA, Yasuhiro TAKASHIMA, Shin'ichi WAKABAYASHI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | For prototyping large ASICs, multi-FPGA systems, which consist of multiple FPGAs, are used. When using such a system, the target circuit is partitioned into FPGAs. Since the number of I/O pins of an FPGA is limited, connecting inter-FPGA I/O signals is often difficult. Thus, time-multiplexed I/Os are used. However, since they have much laeger delay than normal I/Os, they decrease the system clock frequency. To improve the frequency, an existing method employs both of time-multiplexed and non time-multiplexed I/Os, simultaneously, and selects the best signals to be time-multiplexed. However, the method can handle only limited system topologies in which all the pairs of FPGAs are directly connected by wires on the PCB. In this study, to handle various system topologies, we apply the existing method by giving an indirect route to an inter-FPGA signal whose source and destination FPGAs have no direct wires. We tested our proposed method and some system topologies to evaluate how they affect the system speed. The minimum system clock periods were improved by 30.8% on average. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multi-FPGA system / prototyping / time-multiplexed I/O |
| Paper # | RECONF2014-23 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2014/9/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Time-division Multiplexing Method of Inter-FPGA Signals for Multi-FPGA Systems with Various Topologies |
| Sub Title (in English) | |
| Keyword(1) | multi-FPGA system |
| Keyword(2) | prototyping |
| Keyword(3) | time-multiplexed I/O |
| 1st Author's Name | Masato INAGI |
| 1st Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University() |
| 2nd Author's Name | Yuichi NAKAMURA |
| 2nd Author's Affiliation | Green Platform Research Labs., NEC Corporation |
| 3rd Author's Name | Yasuhiro TAKASHIMA |
| 3rd Author's Affiliation | Faculty of Environmental Engineering, The University of Kitakyushu |
| 4th Author's Name | Shin'ichi WAKABAYASHI |
| 4th Author's Affiliation | Graduate School of Information Sciences, Hiroshima City University |
| Date | 2014-09-18 |
| Paper # | RECONF2014-23 |
| Volume (vol) | vol.114 |
| Number (no) | 223 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |