Presentation 2014-09-18
A study of run-time fault detection mechanism for fault-tolerant FPGAs
Kentaro FUJISAWA, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI,
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Abstract(in English) The fault detection is very important for high reliability system LSI. In this paper, we propose a dynamic fault detection mechanism for the fault-tolerant FPGA, which utilizing spare tile resources to detect faults without stopping the circuit. The evaluation results show the proposed fault-tolerant FPGA has a 100% success rate on the dynamic fault detection in 18.5 cycles on average. In addition, the area overhead is only 1.7% when compared to the base fault-tolerant FPGA.
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Keyword(in English) FPGA / Fault detection
Paper # RECONF2014-19
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Committee RECONF
Conference Date 2014/9/11(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) A study of run-time fault detection mechanism for fault-tolerant FPGAs
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) Fault detection
1st Author's Name Kentaro FUJISAWA
1st Author's Affiliation Graduate School of Sience and Technology, Kumamoto University()
2nd Author's Name Motoki AMAGASAKI
2nd Author's Affiliation Graduate School of Sience and Technology, Kumamoto University
3rd Author's Name Masahiro IIDA
3rd Author's Affiliation Graduate School of Sience and Technology, Kumamoto University
4th Author's Name Morihiro KUGA
4th Author's Affiliation Graduate School of Sience and Technology, Kumamoto University
5th Author's Name Toshinori SUEYOSHI
5th Author's Affiliation Graduate School of Sience and Technology, Kumamoto University
Date 2014-09-18
Paper # RECONF2014-19
Volume (vol) vol.114
Number (no) 223
Page pp.pp.-
#Pages 6
Date of Issue