| Presentation | 2014-07-21 Digital Circuit Implementation of a Cost Calculation for Partial-update Exponential Chaotic Tabu Search Hardware Systems Takeshi MIURA, Masato OZAWA, Takemori ORIMA, Yoshihiko HORIO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The exponential chaotic tabu search is an efficient meta-heuristic algorithm for combinatorial optimization problems. Based on this algorithm, we proposed a partial-update exponential chaotic tabu search algorithm, suitable for a compact and efficient hardware implementation. In hardware implementation of the partial-update exponential chaotic tabu search system to solve a quadratic assignment problem (QAP), we will use a digital circuit to calculate the value of the cost function of the QAP, because an analog circuit will have difficulty for this calculation. However, the digital circuitry processes sequentially, so that the digital calculation would be a bottleneck for the speed of the system. In this paper, we propose a quick cost calculation method with digital circuitry. We compare a DSP and a FPGA to implement the cost calculation. As a result, we show that the FPGA with pipeline processing is more feasible than the DSP. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Combinatorial Optimization Problem / Quadratic Assignment Problem / Chaotic Tabu Search / Chaotic Neural Network / Field-Programmable Gate Array(FPGA) |
| Paper # | NLP2014-34 |
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| Conference Information | |
| Committee | NLP |
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| Conference Date | 2014/7/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Nonlinear Problems (NLP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Digital Circuit Implementation of a Cost Calculation for Partial-update Exponential Chaotic Tabu Search Hardware Systems |
| Sub Title (in English) | |
| Keyword(1) | Combinatorial Optimization Problem |
| Keyword(2) | Quadratic Assignment Problem |
| Keyword(3) | Chaotic Tabu Search |
| Keyword(4) | Chaotic Neural Network |
| Keyword(5) | Field-Programmable Gate Array(FPGA) |
| 1st Author's Name | Takeshi MIURA |
| 1st Author's Affiliation | Graduate School of Engineering, Tokyo Denki University() |
| 2nd Author's Name | Masato OZAWA |
| 2nd Author's Affiliation | Graduate School of Engineering, Tokyo Denki University |
| 3rd Author's Name | Takemori ORIMA |
| 3rd Author's Affiliation | Graduate School of Engineering, Tokyo Denki University |
| 4th Author's Name | Yoshihiko HORIO |
| 4th Author's Affiliation | Graduate School of Engineering, Tokyo Denki University |
| Date | 2014-07-21 |
| Paper # | NLP2014-34 |
| Volume (vol) | vol.114 |
| Number (no) | 145 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |