Presentation 2014-08-05
Area-Efficient and Low-Power SAR ADC with Dynamic Comparator Threshold Configuring by Source Voltage Shifting
Masaki YONEKURA, Kentaro YOSHIOKA, Hiroki ISHIKURO,
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Abstract(in English) An extremely low power and area efficient threshold configuring ADC (TC-ADC) is proposed. The threshold configuring comparator (TCC) performs a binary search and only 1b-DAC is required. 5b conversion is carried out by TCC with source voltage shifting technique. Additional 2b resolution is achieved by the proposed threshold interpolation (TI) technique with only 15% power overhead. Prototype ADC in 40nm CMOS occupies a core area of only 0.0038mm^2 and when calibration circuit included, 0.0058 mm^2. With a supply voltage of 0.7V, the ADC achieves 7.0 ENOB with 24MS/s. Peak FoM of 9.8fJ/conv. is obtained at 0.5V supply, which is over 15x improvement compared with conventional TC-ADC.
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Keyword(in English) Successive Approximation ADC / Threshold Configuring / Source Voltage Shifting
Paper # SDM2014-82,ICD2014-51
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Committee ICD
Conference Date 2014/7/28(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Area-Efficient and Low-Power SAR ADC with Dynamic Comparator Threshold Configuring by Source Voltage Shifting
Sub Title (in English)
Keyword(1) Successive Approximation ADC
Keyword(2) Threshold Configuring
Keyword(3) Source Voltage Shifting
1st Author's Name Masaki YONEKURA
1st Author's Affiliation Graduate Course Science and Engineering, Keio University()
2nd Author's Name Kentaro YOSHIOKA
2nd Author's Affiliation Graduate Course Science and Engineering, Keio University
3rd Author's Name Hiroki ISHIKURO
3rd Author's Affiliation Graduate Course Science and Engineering, Keio University
Date 2014-08-05
Paper # SDM2014-82,ICD2014-51
Volume (vol) vol.114
Number (no) 175
Page pp.pp.-
#Pages 5
Date of Issue