| Presentation | 2014-08-05 Low-Power and High-Speed Nonvolatile FPGA by Adjacent Integration of MONOS/Logic and Novel Programming Scheme Koichiro ZAITSU, Kosuke TATSUMURA, Mari MATSUMOTO, Masato ODA, Shinobu FUJITA, Shinichi YASUDA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Novel nonvolatile programmable switch for low-power and high-speed FPGA where MONOS flash is adjacently integrated to CMOS logic is demonstrated. The MONOS transistors and low-voltage switching transistors are fabricated close to each other without deteriorating each performance. Furthermore, memory programming scheme is optimized to realize selective writing with no damage in the switching transistors. MONOS-based configuration memory has a half area of conventional SRAM, and it can be placed in each block in FPGA. That enables efficient power gating that offers low-power FPGA operation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / MONOS flash memory / Nonvolatile memory / Low power |
| Paper # | SDM2014-75,ICD2014-44 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2014/7/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low-Power and High-Speed Nonvolatile FPGA by Adjacent Integration of MONOS/Logic and Novel Programming Scheme |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | MONOS flash memory |
| Keyword(3) | Nonvolatile memory |
| Keyword(4) | Low power |
| 1st Author's Name | Koichiro ZAITSU |
| 1st Author's Affiliation | Corporate R&D Center, Toshiba Corpotation() |
| 2nd Author's Name | Kosuke TATSUMURA |
| 2nd Author's Affiliation | Corporate R&D Center, Toshiba Corpotation |
| 3rd Author's Name | Mari MATSUMOTO |
| 3rd Author's Affiliation | Corporate R&D Center, Toshiba Corpotation |
| 4th Author's Name | Masato ODA |
| 4th Author's Affiliation | Corporate R&D Center, Toshiba Corpotation |
| 5th Author's Name | Shinobu FUJITA |
| 5th Author's Affiliation | Corporate R&D Center, Toshiba Corpotation |
| 6th Author's Name | Shinichi YASUDA |
| 6th Author's Affiliation | Corporate R&D Center, Toshiba Corpotation |
| Date | 2014-08-05 |
| Paper # | SDM2014-75,ICD2014-44 |
| Volume (vol) | vol.114 |
| Number (no) | 175 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |