Presentation | 2014-08-04 A 28nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor with 2GHz Cores and Low-Power 1GHz Cores Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper presents power management and low power techniques of our heterogeneous quad/octa-core mobile application processor (AP). This AP has a combination of high-performance 2 GHz cores and energy-efficient 1 GHz cores. The maximum performance in the octa-core configuration is 35,600 DMIPS. The key design highlights are: 1) Using a dedicated PLL and H-tree clock in the high-performance CPU achieves both 2GHz operation and reduced dynamic power. 2) A low-leakage SRAM in a 28nm High-k/MG process is used and the leakage current of the peripheral circuits of the SRAM macro is optimized via multiple threshold voltages (Vt) and gate lengths (Lg), result in 24% leakage reduction of L1 cache. 3) The effects of process and voltage variations are accurately corrected by an on-chip process sensor and direct sensing of the voltage in the power mesh of the chip. 20% dynamic power reduction, 29% leakage power reduction and 40mV improvement of minimum operation voltage are achieved. 4) An enhanced CPU clock control mechanism is employed, which uses an on-chip delay sensor to reduce AC IR drop. 5) The heterogeneous CPU architecture maintains high performance even during thermal throttling. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | 28nm / Heterogeneous CPU architecture / H-tree clock structure / Multi-Vt / Multi-Lg / Adaptive voltage scaling(AVS) / Dynamic Frequency Scaling(DFS) / Thermal control technique |
Paper # | SDM2014-64,ICD2014-33 |
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Conference Information | |
Committee | ICD |
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Conference Date | 2014/7/28(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A 28nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor with 2GHz Cores and Low-Power 1GHz Cores |
Sub Title (in English) | |
Keyword(1) | 28nm |
Keyword(2) | Heterogeneous CPU architecture |
Keyword(3) | H-tree clock structure |
Keyword(4) | Multi-Vt |
Keyword(5) | Multi-Lg |
Keyword(6) | Adaptive voltage scaling(AVS) |
Keyword(7) | Dynamic Frequency Scaling(DFS) |
Keyword(8) | Thermal control technique |
1st Author's Name | Mitsuhiko Igarashi |
1st Author's Affiliation | Renesas Electronics Corporation() |
2nd Author's Name | Toshifumi Uemura |
2nd Author's Affiliation | Renesas Electronics Corporation |
3rd Author's Name | Ryo Mori |
3rd Author's Affiliation | Renesas Electronics Corporation |
4th Author's Name | Hiroshi Kishibe |
4th Author's Affiliation | Renesas Electronics Corporation |
5th Author's Name | Masaaki Taniguchi |
5th Author's Affiliation | Renesas Electronics Corporation |
6th Author's Name | Kohei Wakahara |
6th Author's Affiliation | Renesas Electronics Corporation |
7th Author's Name | Toshiharu Saito |
7th Author's Affiliation | Renesas Electronics Corporation |
8th Author's Name | Masaki Fujigaya |
8th Author's Affiliation | Renesas Electronics Corporation |
9th Author's Name | Kazuki Fukuoka |
9th Author's Affiliation | Renesas Electronics Corporation |
10th Author's Name | Koji Nii |
10th Author's Affiliation | Renesas Electronics Corporation |
11th Author's Name | Takeshi Kataoka |
11th Author's Affiliation | Renesas Electronics Corporation |
12th Author's Name | Toshihiro Hattori |
12th Author's Affiliation | Renesas Electronics Corporation |
Date | 2014-08-04 |
Paper # | SDM2014-64,ICD2014-33 |
Volume (vol) | vol.114 |
Number (no) | 175 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |