| Presentation | 2014-08-22 Opto-electronic hybrid integrated chip packaging technology for silicon photonic platform using gold-stud bump bonding Mitsuo USUI, Kotaro TAKEDA, Hirooki HIRATA, Hiroshi FUKUDA, Tai TSUCHIZAWA, Hidetaka NISHI, Rai KOU, Tatsuro HIRAKI, Kentaro HONDA, Masashi NOGAWA, Koji YAMADA, Tsuyoshi YAMAMOTO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We propose a new solder-free and low-temperature (200℃ or less) flip-chip integration technology for silicon photonic platforms. Gold (Au) stud bumps are arranged facing each other on a substrate and a chip. Plastic deformation when the bumps are heated and pressed achieves Au-Au bonding. We measured mechanical and electrical characteristics (bond strength, electrical resistance, and high-frequency characteristics) of test samples fabricated by using this technology and confirmed good performance. The bonding strength exceeds the strength requirement of MIL-STD-883J, Method 2019. The electrical resistance at the bump connection is 2.3 mΩ/bump, which is low enough. The frequency response (S21) is flat and return loss (S11) is larger than 20 dB in the frequency range of up to 40 GHz. Further, we fabricated a 4-ch-WDM receiver using this technology and confirmed that it has good performance at 25-Gbit/s operation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Si photonics / flip-chip bonding / gold (Au) stud bump / Au-Au bonding / plastic deformation / packaging technology |
| Paper # | R2014-45,EMD2014-50,CPM2014-65,OPE2014-75,LQE2014-49 |
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| Conference Information | |
| Committee | CPM |
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| Conference Date | 2014/8/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Component Parts and Materials (CPM) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Opto-electronic hybrid integrated chip packaging technology for silicon photonic platform using gold-stud bump bonding |
| Sub Title (in English) | |
| Keyword(1) | Si photonics |
| Keyword(2) | flip-chip bonding |
| Keyword(3) | gold (Au) stud bump |
| Keyword(4) | Au-Au bonding |
| Keyword(5) | plastic deformation |
| Keyword(6) | packaging technology |
| 1st Author's Name | Mitsuo USUI |
| 1st Author's Affiliation | NTT Device Innovation Center, NTT Corporation() |
| 2nd Author's Name | Kotaro TAKEDA |
| 2nd Author's Affiliation | NTT Device Technology Laboratories, NTT Corporation |
| 3rd Author's Name | Hirooki HIRATA |
| 3rd Author's Affiliation | NTT Device Innovation Center, NTT Corporation |
| 4th Author's Name | Hiroshi FUKUDA |
| 4th Author's Affiliation | NTT Device Innovation Center, NTT Corporation |
| 5th Author's Name | Tai TSUCHIZAWA |
| 5th Author's Affiliation | NTT Device Innovation Center, NTT Corporation |
| 6th Author's Name | Hidetaka NISHI |
| 6th Author's Affiliation | NTT Device Technology Laboratories, NTT Corporation |
| 7th Author's Name | Rai KOU |
| 7th Author's Affiliation | NTT Device Technology Laboratories, NTT Corporation |
| 8th Author's Name | Tatsuro HIRAKI |
| 8th Author's Affiliation | NTT Device Technology Laboratories, NTT Corporation |
| 9th Author's Name | Kentaro HONDA |
| 9th Author's Affiliation | NTT Device Technology Laboratories, NTT Corporation |
| 10th Author's Name | Masashi NOGAWA |
| 10th Author's Affiliation | NTT Device Innovation Center, NTT Corporation |
| 11th Author's Name | Koji YAMADA |
| 11th Author's Affiliation | NTT Device Technology Laboratories, NTT Corporation |
| 12th Author's Name | Tsuyoshi YAMAMOTO |
| 12th Author's Affiliation | NTT Device Technology Laboratories, NTT Corporation |
| Date | 2014-08-22 |
| Paper # | R2014-45,EMD2014-50,CPM2014-65,OPE2014-75,LQE2014-49 |
| Volume (vol) | vol.114 |
| Number (no) | 185 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |