Presentation 2014-07-23
Improvement of 64-kb Josephson-CMOS Hybrid Memories toward Their Complete Operation
Yuta SASAKI, Xizhu PENG, Yuki YAMANASHI, Nobuyuki YOSHIKAWA,
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Abstract(in English) We are developing a Josephson-CMOS hybrid memory, which enables sub-nanosecond access time, in order to overcome a memory bottleneck in single-flux-quantum (SFQ) digital systems. In this study, we improved the robustness of the Josephson-CMOS interface for realizing the complete operation of the 64-kb hybrid memory. One problem in our interface circuits is the interaction between the AC bias current for Josephson latching drivers with the SFQ circuits. We have reduced the interaction by using partially separated ground planes and magnetic-shielding structures for the SFQ circuits.
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Keyword(in English) Superconducting integrated circuits / Josephson junctions / CMOS / SFQ / Memory
Paper # SCE2014-33
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Committee SCE
Conference Date 2014/7/16(1days)
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Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Improvement of 64-kb Josephson-CMOS Hybrid Memories toward Their Complete Operation
Sub Title (in English)
Keyword(1) Superconducting integrated circuits
Keyword(2) Josephson junctions
Keyword(3) CMOS
Keyword(4) SFQ
Keyword(5) Memory
1st Author's Name Yuta SASAKI
1st Author's Affiliation Graduate School of Engineering, Yokohama National University()
2nd Author's Name Xizhu PENG
2nd Author's Affiliation Graduate School of Engineering, Yokohama National University
3rd Author's Name Yuki YAMANASHI
3rd Author's Affiliation Graduate School of Engineering, Yokohama National University
4th Author's Name Nobuyuki YOSHIKAWA
4th Author's Affiliation Graduate School of Engineering, Yokohama National University
Date 2014-07-23
Paper # SCE2014-33
Volume (vol) vol.114
Number (no) 147
Page pp.pp.-
#Pages 6
Date of Issue