Presentation 2014-07-23
Design and Evaluation of the 4-bit Parallel Bit-Slice-ALU
Kensuke TAKATA, Masamitsu TANAKA, Akira FUJIMAKI, Kang-Ming TANG, Kazuyoshi TAKAGI, Naofumi TAKAGI,
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Abstract(in English) In our demonstrated SFQ microprocessor design, a bit serial architecture has been used up to now. In order to increase the performance of the microprocessor, we designed a bit-slice adder as we kept introduction of bit-slice architecture in mind. In this paper, we report design of a 4-bit parallel bit-slice ALU using AIST 10 kA/cm^2 niobium advanced process, and demonstration of its high-speed operation.
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Keyword(in English) SFQ circuit / 10kA/cm2 process / 4-bit parallel bit-slice-ALU
Paper # SCE2014-25
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Committee SCE
Conference Date 2014/7/16(1days)
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Registration To Superconductive Electronics (SCE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Design and Evaluation of the 4-bit Parallel Bit-Slice-ALU
Sub Title (in English)
Keyword(1) SFQ circuit
Keyword(2) 10kA/cm2 process
Keyword(3) 4-bit parallel bit-slice-ALU
1st Author's Name Kensuke TAKATA
1st Author's Affiliation Department of Quantum Engineering, Nagoya University()
2nd Author's Name Masamitsu TANAKA
2nd Author's Affiliation Department of Quantum Engineering, Nagoya University
3rd Author's Name Akira FUJIMAKI
3rd Author's Affiliation Department of Quantum Engineering, Nagoya University
4th Author's Name Kang-Ming TANG
4th Author's Affiliation Graduate School of Informatics, Kyoto University
5th Author's Name Kazuyoshi TAKAGI
5th Author's Affiliation Graduate School of Informatics, Kyoto University
6th Author's Name Naofumi TAKAGI
6th Author's Affiliation Graduate School of Informatics, Kyoto University
Date 2014-07-23
Paper # SCE2014-25
Volume (vol) vol.114
Number (no) 147
Page pp.pp.-
#Pages 6
Date of Issue