Presentation 2014-07-31
Effect of Sampling Jitter on Performance of Full-Duplex Radio Transceiver
Ville SYRJALA, Koji YAMAMOTO,
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Abstract(in English) Recent literature has proven that sampling jitter can be a problem in full-duplex radio transceivers. In this technical report, two different transceiver structures are proposed to mitigate the effect of the sampling jitter in full-duplex radio transceivers. In the first structure, reference analog-to-digital converter (ADC), that uses the same clock signal as the actual ADC at the receiver, is used to generate similar sampling jitter effect to a reference signal. This reference signal is then used in sampling jitter mitigation. In the second structure, the same timing signal is fed to the digital-to-analog converter (DAC) in the transmitter and to the ADC at the receiver. In this structure, the timing errors partially cancel each other. In the simulations, it is shown that the performance of the proposed structures for sampling jitter mitigation is superior compared to the prior sampling jitter mitigation techniques.
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Keyword(in English) Full-duplex radios / self-interference / sampling jitter / mitigation
Paper # RCC2014-44,NS2014-64,RCS2014-116,SR2014-45,ASN2014-63
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Committee RCC
Conference Date 2014/7/23(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Effect of Sampling Jitter on Performance of Full-Duplex Radio Transceiver
Sub Title (in English)
Keyword(1) Full-duplex radios
Keyword(2) self-interference
Keyword(3) sampling jitter
Keyword(4) mitigation
1st Author's Name Ville SYRJALA
1st Author's Affiliation Graduate School of Informatics, Kyoto University()
2nd Author's Name Koji YAMAMOTO
2nd Author's Affiliation Graduate School of Informatics, Kyoto University
Date 2014-07-31
Paper # RCC2014-44,NS2014-64,RCS2014-116,SR2014-45,ASN2014-63
Volume (vol) vol.114
Number (no) 162
Page pp.pp.-
#Pages 4
Date of Issue