| Presentation | 2014-07-11 A Floorplan-driven High-Level Synthesis Algorithm for Reducing Multiplexer Inputs Targeting FPGAs Koichi FUJIWARA, Shinya ABE, Kazushi KAWAMURA, Masao YANAGISAWA, Nozomu TOGAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, high-level synthesis (HLS) techniques for FPGA designs are required in situations when it is need to improve specifications in a short time such as computerized stock tradings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-aware HLS algorithm for reducing multiplexer inputs targeting FPGA designs. By utilizing a distirbuted-register architecture called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer inputs, we propose a novel binding methods called datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 33% and 13% on average compared with the conventional approach. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | high-level synthesis (HLS) / FPGA / multiplexer / floorplan / interconnection delay |
| Paper # | CAS2014-41,VLD2014-50,SIP2014-62,MSS2014-41,SIS2014-41 |
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| Committee | MSS |
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| Conference Date | 2014/7/2(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Mathematical Systems Science and its applications(MSS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Floorplan-driven High-Level Synthesis Algorithm for Reducing Multiplexer Inputs Targeting FPGAs |
| Sub Title (in English) | |
| Keyword(1) | high-level synthesis (HLS) |
| Keyword(2) | FPGA |
| Keyword(3) | multiplexer |
| Keyword(4) | floorplan |
| Keyword(5) | interconnection delay |
| 1st Author's Name | Koichi FUJIWARA |
| 1st Author's Affiliation | Grad. of Computer Science and Communications Engineering, Waseda University() |
| 2nd Author's Name | Shinya ABE |
| 2nd Author's Affiliation | Grad. of Computer Science and Communications Engineering, Waseda University |
| 3rd Author's Name | Kazushi KAWAMURA |
| 3rd Author's Affiliation | Grad. of Computer Science and Communications Engineering, Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Grad. of Computer Science and Communications Engineering, Waseda University |
| 5th Author's Name | Nozomu TOGAWA |
| 5th Author's Affiliation | Grad. of Computer Science and Communications Engineering, Waseda University |
| Date | 2014-07-11 |
| Paper # | CAS2014-41,VLD2014-50,SIP2014-62,MSS2014-41,SIS2014-41 |
| Volume (vol) | vol.114 |
| Number (no) | 125 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |