| Presentation | 2014-07-11 Write Reduction of Internal Registers for Non-volatile RISC Processors Tomoya GOTO, Masao YANAGISAWA, Shinji KIMURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently next-generation non-volatile memories based on MTJ (Magnetic Tunnel Junction) have been paid attention because of their enough endurance and fast access speed. The access speed is comparable with that of CMOS memory devices but their writing energy is far larger than the energy of CMOS memory devices. So the reduction of writing operations is very important. In this study, we propose write-reduction methods depending on the types of internal registers for RISC processors. By considering the types, the control circuit can be reduced. For the register file, write operations are reduced by using "write aware flags" and "sign extension flags". For the program counter, write operations are reduced by using "XOR-based comparison" and "carry detection". The proposed method is applied to the MIPS32 processor and the write activity has been evaluated using a simulator. The write activity can be reduced about 93.1-93.8% on register files and about 54.5-56.8% on the program counter. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Next-generation non-volatile memory / MRAM (Magnetoresistive RAM) / non-volatile register file / non-volatile program counter / XOR-based clock gating control |
| Paper # | CAS2014-40,VLD2014-49,SIP2014-61,MSS2014-40,SIS2014-40 |
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| Conference Information | |
| Committee | MSS |
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| Conference Date | 2014/7/2(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Mathematical Systems Science and its applications(MSS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Write Reduction of Internal Registers for Non-volatile RISC Processors |
| Sub Title (in English) | |
| Keyword(1) | Next-generation non-volatile memory |
| Keyword(2) | MRAM (Magnetoresistive RAM) |
| Keyword(3) | non-volatile register file |
| Keyword(4) | non-volatile program counter |
| Keyword(5) | XOR-based clock gating control |
| 1st Author's Name | Tomoya GOTO |
| 1st Author's Affiliation | Graduate School of Electronic and Photonic Systems, Waseda University() |
| 2nd Author's Name | Masao YANAGISAWA |
| 2nd Author's Affiliation | Graduate School of Electronic and Photonic Systems, Waseda University |
| 3rd Author's Name | Shinji KIMURA |
| 3rd Author's Affiliation | Graduate School of Information, Production and Systems, Waseda University |
| Date | 2014-07-11 |
| Paper # | CAS2014-40,VLD2014-49,SIP2014-61,MSS2014-40,SIS2014-40 |
| Volume (vol) | vol.114 |
| Number (no) | 125 |
| Page | pp.pp.- |
| #Pages | 6 |
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