| Presentation | 2014-07-11 Accelerating Boolean Matching of LUT-based Circuits using CEGAR method Yusuke MATSUNAGA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes an accelerating technique for Boolean matching of LUT-based circuits, which is based on CEGAR (counter example guided abstraction refinement) method. CEGAR reduces the search space drastically both on SAT and UNSAT instances. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | logic synthesis / technology mapping / FPGA / Boolean matching / CEGAR / SAT |
| Paper # | CAS2014-38,VLD2014-47,SIP2014-59,MSS2014-38,SIS2014-38 |
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| Conference Information | |
| Committee | MSS |
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| Conference Date | 2014/7/2(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Mathematical Systems Science and its applications(MSS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Accelerating Boolean Matching of LUT-based Circuits using CEGAR method |
| Sub Title (in English) | |
| Keyword(1) | logic synthesis |
| Keyword(2) | technology mapping |
| Keyword(3) | FPGA |
| Keyword(4) | Boolean matching |
| Keyword(5) | CEGAR |
| Keyword(6) | SAT |
| 1st Author's Name | Yusuke MATSUNAGA |
| 1st Author's Affiliation | Faculty of Information Science and Electorical Engineering, Kyushu University() |
| Date | 2014-07-11 |
| Paper # | CAS2014-38,VLD2014-47,SIP2014-59,MSS2014-38,SIS2014-38 |
| Volume (vol) | vol.114 |
| Number (no) | 125 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |