Presentation 2014-06-12
Implementation of a RISC Processor with a Complex Instruction Accelerator : Return to a CISC
Ryota SUZUKI, Takefumi MIYOSHI, Hironori NAKAJO,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) In this paper, we propose a RISC processor with an accelerator which can execute a complex instruction with a co-processor function. We have implemented this mechanism into a processor which has a lower compatible subset of MIPS ISA in which existing instructions for a co-processor can be available. The mechanism allows the processor to utilize an accelerator without modification of an assembler and a compiler. We show evaluated performance gain with comparing a conventional RISC processor with our proposed processor.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Hardware Accelerator / Processor architecture / Co-processor / FPGA
Paper # RECONF2014-13
Date of Issue

Conference Information
Committee RECONF
Conference Date 2014/6/4(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Implementation of a RISC Processor with a Complex Instruction Accelerator : Return to a CISC
Sub Title (in English)
Keyword(1) Hardware Accelerator
Keyword(2) Processor architecture
Keyword(3) Co-processor
Keyword(4) FPGA
1st Author's Name Ryota SUZUKI
1st Author's Affiliation Tokyo University of Agriculture and Technology()
2nd Author's Name Takefumi MIYOSHI
2nd Author's Affiliation e-trees.Japan,Inc.
3rd Author's Name Hironori NAKAJO
3rd Author's Affiliation Institute of Engineering, Tokyo University of Agriculture and Technology
Date 2014-06-12
Paper # RECONF2014-13
Volume (vol) vol.114
Number (no) 75
Page pp.pp.-
#Pages 6
Date of Issue