Presentation 2014-06-12
A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis
Koji OKINA, Rie SOEJIMA, Keisuke DOHI, Yuichiro SHIBATA, Kiyoshi OGURI,
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Abstract(in English) In this paper, we propose a framework to assist memory access optimization for stencil computation on an FPGA with high level synthesis tool, MaxCompiler. We implemented a heat conduction simulation and an FDTD electromagnetic field simulation on the proposed framework. As a result, it is shown that an optimization in which the number of data stream is reduced by increasing the memory access per data stream improves the application performance.
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Keyword(in English) FPGA / MaxCompiler / Stencil computation / Heat conduction simulation / FDTD
Paper # RECONF2014-11
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Committee RECONF
Conference Date 2014/6/4(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) MaxCompiler
Keyword(3) Stencil computation
Keyword(4) Heat conduction simulation
Keyword(5) FDTD
1st Author's Name Koji OKINA
1st Author's Affiliation Graduate School of Engineering, Nagasaki University()
2nd Author's Name Rie SOEJIMA
2nd Author's Affiliation Graduate School of Engineering, Nagasaki University
3rd Author's Name Keisuke DOHI
3rd Author's Affiliation Graduate School of Engineering, Nagasaki University
4th Author's Name Yuichiro SHIBATA
4th Author's Affiliation Graduate School of Engineering, Nagasaki University
5th Author's Name Kiyoshi OGURI
5th Author's Affiliation Graduate School of Engineering, Nagasaki University
Date 2014-06-12
Paper # RECONF2014-11
Volume (vol) vol.114
Number (no) 75
Page pp.pp.-
#Pages 6
Date of Issue