| Presentation | 2014-06-12 Three-dimensional FPGA Structure using High-speed Serial Communication Takuya KAJIWARA, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The three-dimensional (3D) integrated circuit technology is expected to continually improve the LSI (Large Scale Integration) performance when the process miniaturization closing to the physical limitation. However, because the TSV (Through Silicon Via) that used to make the inter-layer vertical connection has much larger area than the transistor, there is a tradeoff between the connectivity and the area overhead. Especially the FPGA (Field Programmable Gate Array) requires large amount of routing resources, it is unrealistic to make the same number of connections vertically as horizontal connections. We have proposed a two-layer compact 3D FPGA with the face-down integration (the base FPGA) method in a previous research. In this paper, we stack multiple base FPGAs with the face-up method, and propose inter-layer high-speed communications with TSV serial connections. The proposed architecture improves FPGA performance by using only few TSVs. The evaluation results show that the proposed 3D FPGA reduces 60% area at the maximum when compared with a 2D FPGA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | 3D-FPGA / High speed serial communication / TSV |
| Paper # | RECONF2014-7 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2014/6/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Three-dimensional FPGA Structure using High-speed Serial Communication |
| Sub Title (in English) | |
| Keyword(1) | 3D-FPGA |
| Keyword(2) | High speed serial communication |
| Keyword(3) | TSV |
| 1st Author's Name | Takuya KAJIWARA |
| 1st Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University() |
| 2nd Author's Name | Motoki AMAGASAKI |
| 2nd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 3rd Author's Name | Masahiro IIDA |
| 3rd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 4th Author's Name | Morihiro KUGA |
| 4th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 5th Author's Name | Toshinori SUEYOSHI |
| 5th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| Date | 2014-06-12 |
| Paper # | RECONF2014-7 |
| Volume (vol) | vol.114 |
| Number (no) | 75 |
| Page | pp.pp.- |
| #Pages | 6 |
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