| Presentation | 2014-06-12 An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture Yoshiya KOMATSU, Masanori HARIYAMA, Michitaka KAMEYAMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents an asynchronous high-performance FPGA that combines Four-Phase Dual-Rail (FPDR) protocol and Level-Encoded Dual-Rail (LEDR) protocol. FPDR protocol is employed to achieve small area for logic blocks, while LEDR protocol is employed to obtain high bit rate and low power for data transfer. Each logic block consists of LEDR-FPDR protocol converter, FPDR-LEDR protocol converter and two pipelined FPDR LUTs that alternately operate. The proposed FPGA is designed using the e-Shuttle 65nm CMOS process and the simulation result shows that the throughput is 3.91 GHz. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Asynchronous circuit / reconfigurable VLSI / Four-Phase Dual-Rail (FPDR) protocol / Level-Encoded Dual-Rail (LEDR) protocol / domino logic |
| Paper # | RECONF2014-6 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2014/6/4(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous circuit |
| Keyword(2) | reconfigurable VLSI |
| Keyword(3) | Four-Phase Dual-Rail (FPDR) protocol |
| Keyword(4) | Level-Encoded Dual-Rail (LEDR) protocol |
| Keyword(5) | domino logic |
| 1st Author's Name | Yoshiya KOMATSU |
| 1st Author's Affiliation | Center for Innovative Integrated Electronic Systems, Tohoku University() |
| 2nd Author's Name | Masanori HARIYAMA |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Michitaka KAMEYAMA |
| 3rd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2014-06-12 |
| Paper # | RECONF2014-6 |
| Volume (vol) | vol.114 |
| Number (no) | 75 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |