Presentation | 2013-12-13 Construction of High Quality Delay Test Set Using Fast On-Chip Delay Measurement Kentaroh KATOH, Haruo KOBAYASHI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Today, low power and high speed LSIs such as microprocessors and SoCs are indispensable in various consumer devices and information infrastructures. To meet the needs of the market, further scaling of devices is required. However scaling of devices induces the frequency of the frequency of the timing related errors. In this study, we present a high quality delay test set using fast on-chip delay measurement. This technique is composed of two phases. In the first phase, critical path analysis is performed using on-chip delay measurement with TDC. In the second phase, test set is created with the analysis of critical paths of the first phase. Experimental result shows that the data overhead of the test vector is 13% on average. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Delay Measurement / TDC / LOS / Static Merge |
Paper # | DC2013-70 |
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Committee | DC |
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Conference Date | 2013/12/6(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Construction of High Quality Delay Test Set Using Fast On-Chip Delay Measurement |
Sub Title (in English) | |
Keyword(1) | Delay Measurement |
Keyword(2) | TDC |
Keyword(3) | LOS |
Keyword(4) | Static Merge |
1st Author's Name | Kentaroh KATOH |
1st Author's Affiliation | Dept. of Electrical Engineering, Tsuruoka National College of Technology() |
2nd Author's Name | Haruo KOBAYASHI |
2nd Author's Affiliation | Faculty of Science and Technology, Gunma University |
Date | 2013-12-13 |
Paper # | DC2013-70 |
Volume (vol) | vol.113 |
Number (no) | 353 |
Page | pp.pp.- |
#Pages | 4 |
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