Presentation 2013-12-13
Variable Test-Timing Generation for Built-in Self-Test on FPGA
Yasuo SATO, Munehiro MATSUURA, Hitoshi ARAKAWA, Yousuke MIYAKE, Seiji KAJIHARA,
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Abstract(in English) This paper proposes a variable test-timing generation method that should be used for built-in self-test on FPGA. Application-dependent test for FPGA targets quality improvement in silicon debug or online test; however, as it requires reconfigurations for design for testability, it is difficult to test the original path delay. To tackle this problem, the authors propose a test method that measures the fastest operating speed of the circuit using variable test timing. The paper proposes a variable test-timing generation method that utilizes embedded phase-shift function of PLL.
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Keyword(in English) FPGA / Built-in Self-Test / Variable test-timing / PLL / Phase-shift
Paper # DC2013-69
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Committee DC
Conference Date 2013/12/6(1days)
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Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Variable Test-Timing Generation for Built-in Self-Test on FPGA
Sub Title (in English)
Keyword(1) FPGA
Keyword(2) Built-in Self-Test
Keyword(3) Variable test-timing
Keyword(4) PLL
Keyword(5) Phase-shift
1st Author's Name Yasuo SATO
1st Author's Affiliation Kyushu Institute of Technology:Japan Science and Technology Agency, CREST()
2nd Author's Name Munehiro MATSUURA
2nd Author's Affiliation Kyushu Institute of Technology
3rd Author's Name Hitoshi ARAKAWA
3rd Author's Affiliation Kyushu Institute of Technology
4th Author's Name Yousuke MIYAKE
4th Author's Affiliation Kyushu Institute of Technology:Japan Science and Technology Agency, CREST
5th Author's Name Seiji KAJIHARA
5th Author's Affiliation Kyushu Institute of Technology:Japan Science and Technology Agency, CREST
Date 2013-12-13
Paper # DC2013-69
Volume (vol) vol.113
Number (no) 353
Page pp.pp.-
#Pages 6
Date of Issue