Presentation 2013-11-08
Evaluation of a Dependable Interrupt Interface by Bundled Interrupt Request Lines
Hayato NOMURA, Hajime SHIMADA, Ryotaro KOBAYASHI,
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Abstract(in English) Conventional processors are exposed to not only on-chip transient faults caused by radiation and permanent failures due to electro-migration, but also off-chip transient faults caused by noise and the permanent failures due to solder cracks. In conventional microcontroller, soft/hard-error tolerance is almost not considered around inputs such as interrupt interface. When fault occurs in this portion, it causes unrecoverable processor state destruction. Therefore, we implemented the dependable interrupt interface that is based on redundant interrupt request lines and query to the client device. In addition, we evaluate the amount of binary footprint and the interrupt latency by the redundant configuration.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Dependability / Redundancy / Microcontroller / Interface / Interrupt
Paper # CPSY2013-40
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Committee CPSY
Conference Date 2013/11/1(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Evaluation of a Dependable Interrupt Interface by Bundled Interrupt Request Lines
Sub Title (in English)
Keyword(1) Dependability
Keyword(2) Redundancy
Keyword(3) Microcontroller
Keyword(4) Interface
Keyword(5) Interrupt
1st Author's Name Hayato NOMURA
1st Author's Affiliation Toyohashi University of Technology()
2nd Author's Name Hajime SHIMADA
2nd Author's Affiliation Nagoya University
3rd Author's Name Ryotaro KOBAYASHI
3rd Author's Affiliation Toyohashi University of Technology
Date 2013-11-08
Paper # CPSY2013-40
Volume (vol) vol.113
Number (no) 282
Page pp.pp.-
#Pages 6
Date of Issue