Presentation | 2013-11-28 Automatic synthesis of the inter-processor communication implimentation for hetero multiprocessor systems Yukihito ISHIDA, Yuki ANDO, Shinya HONDA, Hiroaki TAKADA, Masato EDAHIRO, |
---|---|
PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This paper introduces an automatic synthesis technique of inter-processor communication for System-on-chip with heterogeneous multiprocessors. Along with the increase in the use of heterogeneous multiprocessors such as FPGAs with processor cores, the cost for design and implement of the inter-processor communication becomes a problem. Focusing on that typical heterogeneous multiprocessors have inter-processor interrupts and shared memories, we propose an implementation of inter-processor communication using them. In order to increase the design efficiency, we also propose a method that automatically generates the inter-processor communication for target systems. The case study shows that automatically generated inter-processor communication exactly runs on the system with heterogeneous multiprocessors. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | heterogenious / multiprocessor / inter-processor communication / FPGA |
Paper # | RECONF2013-50 |
Date of Issue |
Conference Information | |
Committee | RECONF |
---|---|
Conference Date | 2013/11/20(1days) |
Place (in Japanese) | (See Japanese page) |
Place (in English) | |
Topics (in Japanese) | (See Japanese page) |
Topics (in English) | |
Chair | |
Vice Chair | |
Secretary | |
Assistant |
Paper Information | |
Registration To | Reconfigurable Systems (RECONF) |
---|---|
Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Automatic synthesis of the inter-processor communication implimentation for hetero multiprocessor systems |
Sub Title (in English) | |
Keyword(1) | heterogenious |
Keyword(2) | multiprocessor |
Keyword(3) | inter-processor communication |
Keyword(4) | FPGA |
1st Author's Name | Yukihito ISHIDA |
1st Author's Affiliation | Graduate School of Information Science Nagoya University() |
2nd Author's Name | Yuki ANDO |
2nd Author's Affiliation | Graduate School of Information Science Nagoya University:The Japan Society for the Promotion of Science |
3rd Author's Name | Shinya HONDA |
3rd Author's Affiliation | Graduate School of Information Science Nagoya University |
4th Author's Name | Hiroaki TAKADA |
4th Author's Affiliation | Graduate School of Information Science Nagoya University |
5th Author's Name | Masato EDAHIRO |
5th Author's Affiliation | Graduate School of Information Science Nagoya University |
Date | 2013-11-28 |
Paper # | RECONF2013-50 |
Volume (vol) | vol.113 |
Number (no) | 325 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |