| Presentation | 2013-11-28 Mapping of Java bytecode to virtual CGRA with implementation in FPGA Yuki OGAWA, Motoki AMAGASAKI, Masahiro IIDA, Morihiro KUGA, Toshinori SUEYOSHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In embedded systems, the needs for rapid both low-cost development and high performance has been increasing recently. The reuse of design assets is important technique in embedded systems. However, in the specialized software for execution environment, the reusability is low generally. We propose a technique in order to accelerate software with keeping its reusability. The proposed technique accelerates the software processing speed by employing data path generation from the description style of software code. It is implemented in FPGA after generating a virtual CGRA from software code.In the verification results of using the electromagnetic wave propagation simulation, the execution time is faster by a factor of 960 than software execution by Nios II. This result indicates the possibility that our proposed acceleration technique can realize both the reusability of Java software development assets and the increasing performance. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Java / accelerator / embedded system / coarse grained reconfigurable arrays |
| Paper # | RECONF2013-47 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2013/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Mapping of Java bytecode to virtual CGRA with implementation in FPGA |
| Sub Title (in English) | |
| Keyword(1) | Java |
| Keyword(2) | accelerator |
| Keyword(3) | embedded system |
| Keyword(4) | coarse grained reconfigurable arrays |
| 1st Author's Name | Yuki OGAWA |
| 1st Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University() |
| 2nd Author's Name | Motoki AMAGASAKI |
| 2nd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 3rd Author's Name | Masahiro IIDA |
| 3rd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 4th Author's Name | Morihiro KUGA |
| 4th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 5th Author's Name | Toshinori SUEYOSHI |
| 5th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| Date | 2013-11-28 |
| Paper # | RECONF2013-47 |
| Volume (vol) | vol.113 |
| Number (no) | 325 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |