| Presentation | 2013-11-27 Circuit design for 3D-stacking using TSV interconnects Kenichi Osada, Futoshi Furuta, Kenichi Takeda, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | To improve the performance of 3D-stacking using TSV interconnects, circuit techniques were developed. To improve Z-axis transmission performance, a wafer-to-wafer stacking process for lowering the capacitance of TSV was developed. An "embedded TSV" design for the shorter on-chip wirings was also devised. Z-axis transmission performance was the highest, namely, 15 Tbps/W. TSV circuit model is proposed for circuit design of 3D transmission. Moreover, to reduce the clock skew between the stacked layers arising from global process variations, a 3D clock-synchronization scheme using a reference clock via TSVs was developed. The clock skew between two layers was reduced by 60% using the new clock scheme. We present the first demonstration of two stacked FPGA layers by using wafer-to-wafer via-last Cu-TSV process |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | TSV / 3D / FPGA / Synchronization scheme |
| Paper # | VLD2013-73,CPM2013-117,ICD2013-94,CPSY2013-58,DC2013-39,RECONF2013-41 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2013/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Circuit design for 3D-stacking using TSV interconnects |
| Sub Title (in English) | |
| Keyword(1) | TSV |
| Keyword(2) | 3D |
| Keyword(3) | FPGA |
| Keyword(4) | Synchronization scheme |
| 1st Author's Name | Kenichi Osada |
| 1st Author's Affiliation | Central Research Laboratory, Hitachi, Ltd.() |
| 2nd Author's Name | Futoshi Furuta |
| 2nd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| 3rd Author's Name | Kenichi Takeda |
| 3rd Author's Affiliation | Central Research Laboratory, Hitachi, Ltd. |
| Date | 2013-11-27 |
| Paper # | VLD2013-73,CPM2013-117,ICD2013-94,CPSY2013-58,DC2013-39,RECONF2013-41 |
| Volume (vol) | vol.113 |
| Number (no) | 321 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |