| Presentation | 2013-11-27 Evaluation of Via Programmable Device named VPEX using benchmark circuits Shota Ueguchi, Ryohei Hori, Taku Otani, Masaya Yoshikawa, Takeshi Fujino, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Non-Recurring engineering cost including photo-mask cost increases with LSI process minimization. We have been studied via programmable logic architecture "VPEX" which can configure arbitrary logic functions by changing 3 via layers with other common layers. The latest VPEX architecture named "VPEX3" has a problem of large area penalty because of the wire congestion. In addition, the rising and falling transition time of configured D-FF is slow compared to that of ASIC. In the new architecture named "VPEX4", the size of Logic Element (LE) is increased for implementing rich wiring resources. In addition, VPEX4 has modified the structure of DFF. In this paper, we have compared the performance between VPEX3 and 4 using Design Compiler as logic synthesis tool and Placer and Router CAD dedicated for VPEX. On the other hand, delay time of DFF is verified using Cadence's Spectre. Consequently, the area of VPEX4 was greatly decreased than that of VPEX3 in the large benchmark circuits. On the other hand, delay time and power consumption of VPEX4 is as small as that of VPEX3. Concerning about the speed performance of DFF, the rising and falling time is decreased in the VPEX4 architecture. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Via Programmable / structured ASIC / Exclusive-OR |
| Paper # | VLD2013-72,DC2013-38 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2013/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Via Programmable Device named VPEX using benchmark circuits |
| Sub Title (in English) | |
| Keyword(1) | Via Programmable |
| Keyword(2) | structured ASIC |
| Keyword(3) | Exclusive-OR |
| 1st Author's Name | Shota Ueguchi |
| 1st Author's Affiliation | Faculty of Science and Enginnering, Ritsumeikan University() |
| 2nd Author's Name | Ryohei Hori |
| 2nd Author's Affiliation | Graduate school of Science Engineering, Ritsumeikan University |
| 3rd Author's Name | Taku Otani |
| 3rd Author's Affiliation | Graduate school of Science Engineering, Ritsumeikan University |
| 4th Author's Name | Masaya Yoshikawa |
| 4th Author's Affiliation | Faculty of Science and Engineering, Meijo |
| 5th Author's Name | Takeshi Fujino |
| 5th Author's Affiliation | Faculty of Science and Enginnering, Ritsumeikan University |
| Date | 2013-11-27 |
| Paper # | VLD2013-72,DC2013-38 |
| Volume (vol) | vol.113 |
| Number (no) | 321 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |