| Presentation | 2013-11-27 Improved via programmable structured ASIC VPEX3S : Improvement of basic logic element to improve operation speed Taku Otani, Ryohei Hori, Masaya Yoshikawa, Takeshi Fujino, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have been studying via programmable structured ASIC architecture "VPEX3(Via Programmable Logic using Exclusive-OR Array 3)" which can realize arbitrary logic by customizing only via layer. Our previous research found that VPEX3 cannot achieve the same maximum operation speed as ASIC and other mask programmable device. In this paper, we propose and evaluate a new architecture "VPEX3S". In this architecture, the output drivability of LE is strengthened, and the via resistance between LEs is reduced in order to reduce the critical path delay. From the evaluation using logic synthesis, maximum operating speed of VPEX3S is improved by about 60% than that of VPEX3. On the other hand, the circuit area is estimated to be 50-60% larger than that of VPEX3 from the logic synthesis result,. This is because the LE size has increased to 1.85 times, because of the increase of transistor gate width and the number of vias. However, after placing and routing, implementation area is estimated to be comparative or smaller. This is because the number of routing resources determines the area. As the result, proposed architecture VPEX3S can realize the same speed performance as ASIC, with the 3.3-4 times larger implementation area. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Via Programmable / structured ASIC / Exclusive-OR |
| Paper # | VLD2013-70,DC2013-36 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2013/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Improved via programmable structured ASIC VPEX3S : Improvement of basic logic element to improve operation speed |
| Sub Title (in English) | |
| Keyword(1) | Via Programmable |
| Keyword(2) | structured ASIC |
| Keyword(3) | Exclusive-OR |
| 1st Author's Name | Taku Otani |
| 1st Author's Affiliation | Graduate school of Science Engineering, Ritsumeikan University() |
| 2nd Author's Name | Ryohei Hori |
| 2nd Author's Affiliation | Graduate school of Science Engineering, Ritsumeikan University |
| 3rd Author's Name | Masaya Yoshikawa |
| 3rd Author's Affiliation | Faculty of Science and Engineering, Meijo |
| 4th Author's Name | Takeshi Fujino |
| 4th Author's Affiliation | Faculty of Science and Enginnering, Ritsumeikan University |
| Date | 2013-11-27 |
| Paper # | VLD2013-70,DC2013-36 |
| Volume (vol) | vol.113 |
| Number (no) | 321 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |