Presentation 2013-11-27
A Hardware/Software Simulator for NoC using SystemC and QEMU
Yosuke Kurimoto, Yusuke Fukutsuka, Ittetsu Taniguchi, Hiroyuki Tomiyama,
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Abstract(in English) Network-on-Chip (NoC) is considered as a promising interconnection scheme for many-core System-on-a-Chip (SoC) since it offers better scalability than traditional bus-based interconnection. In this paper, we proposed a fast simulator of NoC architectures using QEMU and Noxim. QEMU is an open-source CPU emulator, and Noxim is an open-source SystemC base NoC simulator for on-chip interconnection network. Experimental results show that proposed simulator successfully simulates a 108 core NoC in a practical time.
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Keyword(in English) Instruction-set simulation / Network-on-Chip / SystemC / Software development support
Paper # VLD2013-69,DC2013-35
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Committee DC
Conference Date 2013/11/20(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Hardware/Software Simulator for NoC using SystemC and QEMU
Sub Title (in English)
Keyword(1) Instruction-set simulation
Keyword(2) Network-on-Chip
Keyword(3) SystemC
Keyword(4) Software development support
1st Author's Name Yosuke Kurimoto
1st Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University()
2nd Author's Name Yusuke Fukutsuka
2nd Author's Affiliation College of Science and Engineering, Ritsumeikan University
3rd Author's Name Ittetsu Taniguchi
3rd Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University
4th Author's Name Hiroyuki Tomiyama
4th Author's Affiliation Graduate School of Science and Engineering, Ritsumeikan University
Date 2013-11-27
Paper # VLD2013-69,DC2013-35
Volume (vol) vol.113
Number (no) 321
Page pp.pp.-
#Pages 6
Date of Issue