| Presentation | 2013/11/20 A Logic Simulation Method using FPGA Natsuki Matsumoto, Michiaki Muraoka, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, a hardware algorithm of the logic simulation using the leveled method is proposed. To speed up the algorithm, the logic evaluation part of the hardware algorithm is parallelized. Then this accelerates the evaluation speed of the logic gates on the logic level of the logic circuit by the parallelization. The parallel logic simulation algorithm was implemented in the FPGA, and the performance of the FPGA was evaluated. As the result of the evaluation of the timing simulation, the speed of the proposed hardware algorithm achieved approximately 10 times faster than that of a fast commercial logic simulator using 30,000 gates. In addition, when it is applied to larger scale circuits such as one million gate circuits, it is estimated to be 20 times faster respectively. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Logic Simulation / Parallel Processing / Parallel Algorithm / LSI |
| Paper # | Vol.2013-SLDM-163 No.11 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2013/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Logic Simulation Method using FPGA |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Logic Simulation |
| Keyword(3) | Parallel Processing |
| Keyword(4) | Parallel Algorithm |
| Keyword(5) | LSI |
| 1st Author's Name | Natsuki Matsumoto |
| 1st Author's Affiliation | Information Science Division, Graduate School of Science, Kochi University() |
| 2nd Author's Name | Michiaki Muraoka |
| 2nd Author's Affiliation | Information Science Division, Graduate School of Science, Kochi University |
| Date | 2013/11/20 |
| Paper # | Vol.2013-SLDM-163 No.11 |
| Volume (vol) | vol.113 |
| Number (no) | 321 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |