| Presentation | 2013-11-27 Suspicious timing error prediction using check points Hiroaki IGARASHI, Youhua SHI, Masao YANAGISAWA, Nozomu TOGAWA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Due to advance process technologies, timing design of LSIs has become more difficult and the importance of timing error countermeasure techniques is increasing as well. Existing timing error detection/correction methods have difficulties in timing design since they have complex structure. Furthermore, their error correction is realized by re-run operation which results in low throughput. We have proposed a suspicious timing error prediction method (STEP method) which predicts timing error and corrects it with simple structure. STEP is based on checking timing errors by observing several checkpoints on signal paths. Since STEP is a timing error prediction method, we may have false positives and reduction of them is one of the largest problems. In this paper, we propose a method to reduce the false positives to optimize the checkpoints. The experimental results show that an operational frequency is increased by up to 2.4 times and its throughput is improved by up to 45%. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Timing error prediction / robust design / clock gating |
| Paper # | VLD2013-67,DC2013-33 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2013/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Suspicious timing error prediction using check points |
| Sub Title (in English) | |
| Keyword(1) | Timing error prediction |
| Keyword(2) | robust design |
| Keyword(3) | clock gating |
| 1st Author's Name | Hiroaki IGARASHI |
| 1st Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Youhua SHI |
| 2nd Author's Affiliation | Waseda Institute for Advanced Study, Waseda University |
| 3rd Author's Name | Masao YANAGISAWA |
| 3rd Author's Affiliation | Dept. of Electronic and Photonic Systems, Waseda University |
| 4th Author's Name | Nozomu TOGAWA |
| 4th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2013-11-27 |
| Paper # | VLD2013-67,DC2013-33 |
| Volume (vol) | vol.113 |
| Number (no) | 321 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |