| Presentation | 2013-11-27 A Heuristic Design Method for Yield Improvement based on PPCs Shunichi SANAE, Yuko HARA-AZUMI, Shigeru YAMASHITA, Yasuhiko NAKASHIMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A PPC (Partially-Programmable Circuit) is a novel circuit model, which replaces some logic gates with LUTs (Look Up Tables) and adds redundant wires. PPCs have an ability to improve the manufacturing yield by bypassing some faults utilizing the reconfigurability of the LUTs. In this paper, a heuristic method which partitions a circuit into several sub-circuits and optimizes each sub-circuit is proposed for reducing the exploration time of adding the redundant wires. The proposed method is evaluated with two types of LUTs. Comparing with a full search method, our method reduced the exploration time by 92.2% and 90.1% while maintaining the high optimality (on average 89.0% and 100%, respectively), which demonstrates the effectiveness of the proposed method. Furthermore, discussions considering features of benchmark circuits are given. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Yield Improvement / Partially-Programmable Circuit / Optimization |
| Paper # | VLD2013-65,DC2013-31 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2013/11/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Heuristic Design Method for Yield Improvement based on PPCs |
| Sub Title (in English) | |
| Keyword(1) | Yield Improvement |
| Keyword(2) | Partially-Programmable Circuit |
| Keyword(3) | Optimization |
| 1st Author's Name | Shunichi SANAE |
| 1st Author's Affiliation | Nara Institute of Science and Technology() |
| 2nd Author's Name | Yuko HARA-AZUMI |
| 2nd Author's Affiliation | Nara Institute of Science and Technology |
| 3rd Author's Name | Shigeru YAMASHITA |
| 3rd Author's Affiliation | Ritsumeikan University |
| 4th Author's Name | Yasuhiko NAKASHIMA |
| 4th Author's Affiliation | Nara Institute of Science and Technology |
| Date | 2013-11-27 |
| Paper # | VLD2013-65,DC2013-31 |
| Volume (vol) | vol.113 |
| Number (no) | 321 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |