Presentation 2013-11-27
A VLSI algorithm for computing correctly rounded hypotenuse
Hiroyuki YATAKA, Naofumi TAKAGI,
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Abstract(in English) Computation of the hypotenuse (2D euclidean norm) often appears in floating-point arithmetic in computer graphics and scientific computation. It is one of the recommended correctly rounded functions in IEEE754-2008 standard for floating-point arithmetic. In this report, a radix-2 digit-recurrence algorithm for computing the mantissa part of the correctly rounded hypotenuse, which is suitable for VLSI implementation, is proposed. The operand with the higher order of magnitude is used as the initial value of the partial result, and correcting-digits are added to it step by step for obtaining the hypotenuse. A partial product of the square of the other operand is added to the residual, step by step. Through n+2 stages, the hypotenuse is obtained to n+1 binary position with exact remainder, and hence can be rounded correctly. A radix-4 algorithm is also shown.
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Keyword(in English) Hypotenuse / VLSI algorithm / digit-recurrence algorithm / IEEE754 rounding
Paper # VLD2013-61,DC2013-27
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Committee DC
Conference Date 2013/11/20(1days)
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Language ENG
Title (in Japanese) (See Japanese page)
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Title (in English) A VLSI algorithm for computing correctly rounded hypotenuse
Sub Title (in English)
Keyword(1) Hypotenuse
Keyword(2) VLSI algorithm
Keyword(3) digit-recurrence algorithm
Keyword(4) IEEE754 rounding
1st Author's Name Hiroyuki YATAKA
1st Author's Affiliation Graduate school of Informatics, Kyoto University()
2nd Author's Name Naofumi TAKAGI
2nd Author's Affiliation Graduate school of Informatics, Kyoto University
Date 2013-11-27
Paper # VLD2013-61,DC2013-27
Volume (vol) vol.113
Number (no) 321
Page pp.pp.-
#Pages 6
Date of Issue