Presentation 2014-04-25
Fault-Tolerant Logical Integrated Circuits Based on Stochastic Computation
Daisaku KATAGIRI, Naoya ONIZAWA, Takahiro HANYU,
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Abstract(in English) This paper introduces fault-tolerant logical integrated circuits based on stochastic computation. In the stochastic computation realized in a probabilistic domain, a probability is represented by a Bernoulli sequence that consists of a random sequence of bits. If an error occurs that flips a bit in the sequence, the probability is rarely affected because it is represented by the frequency of ones or zeros in the sequence. As a design example, an edge-detection circuit based on stochastic computation is designed using Verilog-HDL that shows comparison results with a conventional edge-detection circuit.
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Keyword(in English) Probabilistic signal processing / image processing / edge detection
Paper # CPSY2014-6,DC2014-6
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Committee DC
Conference Date 2014/4/18(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Fault-Tolerant Logical Integrated Circuits Based on Stochastic Computation
Sub Title (in English)
Keyword(1) Probabilistic signal processing
Keyword(2) image processing
Keyword(3) edge detection
1st Author's Name Daisaku KATAGIRI
1st Author's Affiliation Graduate School of Engineering, Tohoku University()
2nd Author's Name Naoya ONIZAWA
2nd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
3rd Author's Name Takahiro HANYU
3rd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
Date 2014-04-25
Paper # CPSY2014-6,DC2014-6
Volume (vol) vol.114
Number (no) 22
Page pp.pp.-
#Pages 5
Date of Issue