| Presentation | 2014-04-25 Construction of Design Environment for Asynchronous Circuits using DDL Cell Library Masashi IMAI, Hiromasa IGARASHI, Sanshiro KUDO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As the VLSI fabrication technology advances, delay variations due to random process variations, crosstalk, and aging effect, which exhibit random characteristics even in the neighboring components, have been one of main issues. QDI-model-based dual-rail asynchronous circuits are promising implementation against these random variations. However, the dual-rail circuits which are composed by the normal single-rail standard-cell libraries may be twice larger than the corresponding single-rail circuits. In this paper, we propose DDL (Differential Domino Logic) cell libraries and their logic synthesis libraries in order to design high-performance and small-area asynchronous circuits. The cell libraries contain 12 DDL cells, which can implement any function by one of them. We also design three synthesis libraries in the Liberty format and compare them. We will show some evaluation results using the Nangate 45nm process technologies. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Asynchronous circuits / Dual-rail encoding / QDI model / DDL cell library / Logic synthesis / Technology mapping |
| Paper # | CPSY2014-2,DC2014-2 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2014/4/18(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Construction of Design Environment for Asynchronous Circuits using DDL Cell Library |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous circuits |
| Keyword(2) | Dual-rail encoding |
| Keyword(3) | QDI model |
| Keyword(4) | DDL cell library |
| Keyword(5) | Logic synthesis |
| Keyword(6) | Technology mapping |
| 1st Author's Name | Masashi IMAI |
| 1st Author's Affiliation | Hirosaki Unversity() |
| 2nd Author's Name | Hiromasa IGARASHI |
| 2nd Author's Affiliation | Hirosaki Unversity |
| 3rd Author's Name | Sanshiro KUDO |
| 3rd Author's Affiliation | Hirosaki Unversity |
| Date | 2014-04-25 |
| Paper # | CPSY2014-2,DC2014-2 |
| Volume (vol) | vol.114 |
| Number (no) | 22 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |