Presentation 2014-03-04
Advanced Model-Based Hotspot Fix Flow for Layout Optimization with Genetic Algorithm
Shuhei SOTA, Taiga UNO, Masanari KAJIWARA, Chikaaki KODAMA, Hirotaka ICHIKAWA, Ryota ABURADA, Toshiya KOTANI, Kei NAKAGAWA, Tamaki SAITO,
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Abstract(in English) Under the low-k1 lithography process, many hotspots are generated and their reduction is an urgent issue for mass production. Several strategies for hotspots fix (HSF) were proposed so far. Among them, two major strategies are "rule-based HSF" and "pattern matching-based HSF". The former is a simple strategy of expanding the width of narrow patterns and spaces based on pre-determined rule to remove hotspots. However, hotspots unable to remove by this strategy are increasing in recent 32nm and 28nm node. On the other hand, the latter is more effective than the former. This HSF can remove hotspots by replacing the pattern with the corresponding fixed pattern if both patterns are registered in the library. When they are not registered, it is understood that hotspots cannot be removed. Therefore, we propose a new model-based HSF strategy. Our strategy finds minimum width of pattern and minimum space between patterns and tries to remove hotspots by moving edges of the patterns. Genetic algorithm determines appropriately which edges to move and how long. The experimental results show the effectiveness of our strategy.
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Keyword(in English) Lithography / Hotspot / HSF / Genetic algorithm / Model-based HSF
Paper # VLD2013-148
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Conference Information
Committee VLD
Conference Date 2014/2/24(1days)
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Paper Information
Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Advanced Model-Based Hotspot Fix Flow for Layout Optimization with Genetic Algorithm
Sub Title (in English)
Keyword(1) Lithography
Keyword(2) Hotspot
Keyword(3) HSF
Keyword(4) Genetic algorithm
Keyword(5) Model-based HSF
1st Author's Name Shuhei SOTA
1st Author's Affiliation Toshiba Microelectronics Corporation()
2nd Author's Name Taiga UNO
2nd Author's Affiliation Toshiba Corporation Semiconductor & Storage Company
3rd Author's Name Masanari KAJIWARA
3rd Author's Affiliation Toshiba Corporation Semiconductor & Storage Company
4th Author's Name Chikaaki KODAMA
4th Author's Affiliation Toshiba Corporation Semiconductor & Storage Company
5th Author's Name Hirotaka ICHIKAWA
5th Author's Affiliation Toshiba Microelectronics Corporation
6th Author's Name Ryota ABURADA
6th Author's Affiliation Toshiba Corporation Semiconductor & Storage Company
7th Author's Name Toshiya KOTANI
7th Author's Affiliation Toshiba Corporation Semiconductor & Storage Company
8th Author's Name Kei NAKAGAWA
8th Author's Affiliation Toshiba Microelectronics Corporation
9th Author's Name Tamaki SAITO
9th Author's Affiliation Toshiba Microelectronics Corporation
Date 2014-03-04
Paper # VLD2013-148
Volume (vol) vol.113
Number (no) 454
Page pp.pp.-
#Pages 78
Date of Issue