| Presentation | 2014-03-03 Secure scan design using improved random order scans and its evaluations Masaru OYA, Yuta ATOBE, Youhua SHI, Masao YANAGISAWA, Nozomu TOGAWA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Scan test using scan chains is one of the most important DFT techniques. On the other hand, scan-based attacks are reported which can retrieve the secret key in crypto circuits by using scan chains. Secure scan architecture is strongly required to protect scan chains from scan-based attacks. In this paper, we propose an improved version of random order scans as a secure scan architecture. In our improved random order scans, a scan chain is partitioned into multiple sub-chains. The structure of the scan chain changes dynamically by selecting a subchain to scan out using enable signals. We also discuss testability and security of our improved random order scans and demonstrate their effectiveness through implementation results. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | design for testability / scan chains / secure scan architecture / security / testability / area-overhead |
| Paper # | VLD2013-141 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2014/2/24(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Secure scan design using improved random order scans and its evaluations |
| Sub Title (in English) | |
| Keyword(1) | design for testability |
| Keyword(2) | scan chains |
| Keyword(3) | secure scan architecture |
| Keyword(4) | security |
| Keyword(5) | testability |
| Keyword(6) | area-overhead |
| 1st Author's Name | Masaru OYA |
| 1st Author's Affiliation | Dept. Computer Science and Engineering, Waseda University() |
| 2nd Author's Name | Yuta ATOBE |
| 2nd Author's Affiliation | Dept. Computer Science and Engineering, Waseda University |
| 3rd Author's Name | Youhua SHI |
| 3rd Author's Affiliation | Waseda Institute for Advanced Study, Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Dept. Computer Science and Engineering, Waseda University |
| 5th Author's Name | Nozomu TOGAWA |
| 5th Author's Affiliation | Dept. Computer Science and Engineering, Waseda University |
| Date | 2014-03-03 |
| Paper # | VLD2013-141 |
| Volume (vol) | vol.113 |
| Number (no) | 454 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |