Presentation 2014-03-10
Study on a High Precision Simultation Method for LDPC Codes
Akiyoshi HASHIMOTO, Atsushi ISHIKAWA,
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Abstract(in English) We studied on a simulation method which can estimate LDPC codes' frame error rate in high precesion. We assumed the information channel be a BSC, fixed erronous bits and simulated decoding codewords in random errors. Above all, we can estimate frame error rate in the order of 10^<-16> for storage devices.
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Keyword(in English) Low-Density Parity Check Codes / LDPC / simulation / frame error rate / storage devices
Paper # IT2013-65,ISEC2013-94,WBS2013-54
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Committee ISEC
Conference Date 2014/3/3(1days)
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Registration To Information Security (ISEC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Study on a High Precision Simultation Method for LDPC Codes
Sub Title (in English)
Keyword(1) Low-Density Parity Check Codes
Keyword(2) LDPC
Keyword(3) simulation
Keyword(4) frame error rate
Keyword(5) storage devices
1st Author's Name Akiyoshi HASHIMOTO
1st Author's Affiliation Yokohama Research Laboratory, Hitachi, Ltd.()
2nd Author's Name Atsushi ISHIKAWA
2nd Author's Affiliation Information & Telecommunication Systems Company, Hitachi, Ltd.
Date 2014-03-10
Paper # IT2013-65,ISEC2013-94,WBS2013-54
Volume (vol) vol.113
Number (no) 484
Page pp.pp.-
#Pages 4
Date of Issue