Presentation | 2014-03-07 Low-Power IP Lookup LSI Based on Sparse Clustered Networks Naoya ONIZAWA, Warren GROSS, Takahiro HANYU, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In this paper, a novel architecture for low-power IP lookup engines is introduced. The proposed architecture greatly increases memory efficiency by storing associations between IP addresses and their output rules instead of storing these data themselves. The rules can be determined by simple hardware using a few associations read from SRAMs, eliminating a power-hungry brute-force search of input addresses in TCAMs. The proposed hardware is designed under TSMC 65nm CMOS technology and is evaluated using HSPICE to show the energy efficiency compared to a conventional approach. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Associative memory / ternary content-addressable memory (TCAM) / neural networks |
Paper # | CAS2013-123,SIP2013-169,CS2013-136 |
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Committee | CS |
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Conference Date | 2014/2/27(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Communication Systems (CS) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Low-Power IP Lookup LSI Based on Sparse Clustered Networks |
Sub Title (in English) | |
Keyword(1) | Associative memory |
Keyword(2) | ternary content-addressable memory (TCAM) |
Keyword(3) | neural networks |
1st Author's Name | Naoya ONIZAWA |
1st Author's Affiliation | Research Institute of Electrical Communication, Tohoku University() |
2nd Author's Name | Warren GROSS |
2nd Author's Affiliation | McGill University |
3rd Author's Name | Takahiro HANYU |
3rd Author's Affiliation | Research Institute of Electrical Communication, Tohoku University |
Date | 2014-03-07 |
Paper # | CAS2013-123,SIP2013-169,CS2013-136 |
Volume (vol) | vol.113 |
Number (no) | 465 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |