| Presentation | 2014-03-06 Hardware Implementation of Soft Cascaded SVM Classifier Kazutaka TAKEUCHI, Jaehoon YU, Ryusuke MIYAMOTO, Takao ONOYE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | To speed up the object detection without degradation of the accuracy, the following two approaches are proposed: Reducing computational amount and parallel implementation using a specialized hardware engine. A soft cascaded support vector machine drastically reduces computation time for CoHOG-based pedestrian detection. On the other hand, CoHOG-based pedestrian detection has been implemented on FPGA with specialized architecture that drastically reduces hardware resources. However, it is difficult to combine both approaches for accelerating the computation of pedestrian detection. To solve this problem, this paper proposes a novel architecture suitable for object detection with the soft cascaded classifier. The proposed architecture enables high-speed computation of object detection by sharing the operation units, using parallel computation, and pipelining properly that are designed considering the characteristics of the soft cascaded classifier rejecting non-target objects in earlier stages. The proposed architecture can compute 2.7 million sub-windows whose size is 60x120 per second @ 127.7 MHz if it is implemented on a Kintex-7 325 FPGA. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | hardware / parallelization / pipeline / soft cascade / SVM |
| Paper # | SIS2013-58 |
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| Conference Information | |
| Committee | SIS |
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| Conference Date | 2014/2/27(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Smart Info-Media Systems (SIS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Hardware Implementation of Soft Cascaded SVM Classifier |
| Sub Title (in English) | |
| Keyword(1) | hardware |
| Keyword(2) | parallelization |
| Keyword(3) | pipeline |
| Keyword(4) | soft cascade |
| Keyword(5) | SVM |
| 1st Author's Name | Kazutaka TAKEUCHI |
| 1st Author's Affiliation | Graduate School of Information Science and Technology, Osaka University() |
| 2nd Author's Name | Jaehoon YU |
| 2nd Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| 3rd Author's Name | Ryusuke MIYAMOTO |
| 3rd Author's Affiliation | Graduate School of Science and Technology, Meiji University |
| 4th Author's Name | Takao ONOYE |
| 4th Author's Affiliation | Graduate School of Information Science and Technology, Osaka University |
| Date | 2014-03-06 |
| Paper # | SIS2013-58 |
| Volume (vol) | vol.113 |
| Number (no) | 467 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |