Presentation 2014-02-10
Test Data Reduction Method for BIST-Aided Scan Test by Controlling Scan Shift and Partial Reset of Inverter Code
Ryota MORI, Hiroyuki YOTSUYANAGI, Masaki HASHIZUME,
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Abstract(in English) BIST-aided scan test (BAST) has been proposed as one of the techniques that enhances scan-based BIST. The BAST architecture can achieve high fault coverage by applying ATPG patterns to a circuit through the inverter block that flips some bits in random pattern generated by LFSR. In this paper, we propose a test pattern generation method for BAST that controls scan shift and applies partial reset of inverter code to reduce test data. The proposed method can reduce the number of BAST codes required inverter code by partial reset and generate effective LFSR patterns by controlling scanshift. We also show the effectiveness of our method by the experimental results for ISCAS 89 and ITC99 benchmark circuits.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) BAST / test data reduction / test pattern generation
Paper # DC2013-88
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Committee DC
Conference Date 2014/2/3(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Test Data Reduction Method for BIST-Aided Scan Test by Controlling Scan Shift and Partial Reset of Inverter Code
Sub Title (in English)
Keyword(1) BAST
Keyword(2) test data reduction
Keyword(3) test pattern generation
1st Author's Name Ryota MORI
1st Author's Affiliation Graduate School of Advanced Technology and Science, Univ. of Tokushima()
2nd Author's Name Hiroyuki YOTSUYANAGI
2nd Author's Affiliation Institute of Technology and Science, Univ. of Tokushima
3rd Author's Name Masaki HASHIZUME
3rd Author's Affiliation Institute of Technology and Science, Univ. of Tokushima
Date 2014-02-10
Paper # DC2013-88
Volume (vol) vol.113
Number (no) 430
Page pp.pp.-
#Pages 6
Date of Issue