| Presentation | 2014-02-10 A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit Sanae MIZUTANI, Hiroshi IWATA, Ken'ichi YAMAGUCHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With the advances of semiconductor process technologies, synchronous circuits have serious problems of thr clock. Asynchronous circuits can solove the problems of synchronous design. Synchronous-asynchronous converted techniques have been proposed as a method for implementing asynchronous circuits. This paper focuses on testing QDI asynchronous circuits converted from synchronous ones. Previous methods cannot detect faults to be irredundant by converted. We classified the faults to five types, and proposed DFT method in according to the each fault type. In the experimental results the proposed method achieved 100% fault coverage, and the area overhead of the proposed method is evaluated. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | asynchronous circuit / synchronous-asynchronous converted techniques / Quasi Delay Insensitive / design for testability / test generation |
| Paper # | DC2013-81 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2014/2/3(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit |
| Sub Title (in English) | |
| Keyword(1) | asynchronous circuit |
| Keyword(2) | synchronous-asynchronous converted techniques |
| Keyword(3) | Quasi Delay Insensitive |
| Keyword(4) | design for testability |
| Keyword(5) | test generation |
| 1st Author's Name | Sanae MIZUTANI |
| 1st Author's Affiliation | Faculty of Advanced Engineering, Nara National Collage of Technology() |
| 2nd Author's Name | Hiroshi IWATA |
| 2nd Author's Affiliation | Department of Information Engineering, Nara National Collage of Technology |
| 3rd Author's Name | Ken'ichi YAMAGUCHI |
| 3rd Author's Affiliation | Department of Information Engineering, Nara National Collage of Technology |
| Date | 2014-02-10 |
| Paper # | DC2013-81 |
| Volume (vol) | vol.113 |
| Number (no) | 430 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |