Presentation | 2014-02-10 On Feasibility of Delay Detection by Time-to-Digital Converter Embedded in Boundary-Scan Hiroki SAKURAI, Hiroyuki YOTSUYANAGI, Masaki HASHIZUME, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In recent deep sub-micron (DSM) ICs, it is difficult to detect open and short defects since they do not behave like conventional stuck-at fault model and appers as a delay. In order to detect small delay defects, we have proposed TDC(Time-to-Digital Converter) embedded in boundary-scan circuit. An example circuit with TDC embedded in boundary-scan circuit is design and fabricated. In this paper, we evaluate feasibility to detect delay defects using the experimental IC. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | design for testability / delay fault / delay detection circuit / boundary-scan |
Paper # | DC2013-80 |
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Committee | DC |
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Conference Date | 2014/2/3(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | On Feasibility of Delay Detection by Time-to-Digital Converter Embedded in Boundary-Scan |
Sub Title (in English) | |
Keyword(1) | design for testability |
Keyword(2) | delay fault |
Keyword(3) | delay detection circuit |
Keyword(4) | boundary-scan |
1st Author's Name | Hiroki SAKURAI |
1st Author's Affiliation | Graduate School of Advanced Technology and Science, Univ. of Tokushima() |
2nd Author's Name | Hiroyuki YOTSUYANAGI |
2nd Author's Affiliation | Institute of Technology and Science, Univ. of Tokushima |
3rd Author's Name | Masaki HASHIZUME |
3rd Author's Affiliation | Institute of Technology and Science, Univ. of Tokushima |
Date | 2014-02-10 |
Paper # | DC2013-80 |
Volume (vol) | vol.113 |
Number (no) | 430 |
Page | pp.pp.- |
#Pages | 6 |
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