Presentation 2014-01-23
Low Complexity Quasi MLD MIMO Decoder Using 2D Sorter
Thi-Hong TRAN, Reina HONGYO, Yuhei NAGAO, Hiroshi OCHI,
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Abstract(in English) This paper proposes a low complexity quasi Maximum Likelihood Detection (MLD) algorithm and hardware architecture for MIMO system. The hardware circuit is designed for a 4×4 IEEE 802.11n/ac MIMO systems supporting up to 256-QAM. Direct Expansion and two dimensional (2D) sorter are the two key points of the algorithm. In addition, the proposed hardware architecture does not implement either divider or multiplier. As compared to the previous works, our decoder achieves the highest throughput (up to 2.7 Gbps), consumes the least power (56 mW), and obtains the best hardware efficient (15.2 Mbps/Kgate), while achieving high BER performance.
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Keyword(in English) Maximum likelihood detection (MLD) / MIMO decoder / IEEE 802.11n/ac / 256-QAM
Paper # SIP2013-95,RCS2013-265
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Committee RCS
Conference Date 2014/1/16(1days)
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Registration To Radio Communication Systems (RCS)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Low Complexity Quasi MLD MIMO Decoder Using 2D Sorter
Sub Title (in English)
Keyword(1) Maximum likelihood detection (MLD)
Keyword(2) MIMO decoder
Keyword(3) IEEE 802.11n/ac
Keyword(4) 256-QAM
1st Author's Name Thi-Hong TRAN
1st Author's Affiliation Ochi lab, Kyushu Institute of Technology()
2nd Author's Name Reina HONGYO
2nd Author's Affiliation Ochi lab, Kyushu Institute of Technology
3rd Author's Name Yuhei NAGAO
3rd Author's Affiliation Radrix co. ltd.
4th Author's Name Hiroshi OCHI
4th Author's Affiliation Ochi lab, Kyushu Institute of Technology
Date 2014-01-23
Paper # SIP2013-95,RCS2013-265
Volume (vol) vol.113
Number (no) 386
Page pp.pp.-
#Pages 6
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