| Presentation | 2014-01-21 A Prototype Switched-Current Chaotic Neuron Integrated Circuit for the Parallel Updating Chaotic Tabu Search Hardware System Akihito TOYODA, SYU Tanaka, Yosihiko HORIO, Kazuyuki AIHARA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | An exponential chaotic tabu search, in which the tabu search is driven by chaotic neurodynamics, has been proposed and applied to combinatorial optimization problems. However, the hardware cost of the synchronous updating exponential chaotic tabu search increases as the size of the problem increases. Therefore, several modifications such as synchronous and parallel updatings of the neuronal states have been introduced in the exponential chaotic tabu search for efficient implementation with analog/digital hybrid hardware systems. In this paper, we design the chaotic neuron circuit suitable for hardware implementation with the analog inverter-based switched-current (SI) circuit technique. Moreover, we implement the SI chaotic neuron circuit with TSMC 0.18μm CMOS process. The fabricated circuit can control the decay parameter k_r in 8 steps. By adjusting the value of k_r, we can solve any type of problems through the hardware system. From measurement results, we confirm effectiveness of the fabricated SI chaotic neuron integrated circuit. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | combinatorial optimization problem / quadratic assignment problem / chaotic taboo search / chaotic neural network |
| Paper # | NLP2013-140 |
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| Committee | NLP |
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| Conference Date | 2014/1/14(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Nonlinear Problems (NLP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Prototype Switched-Current Chaotic Neuron Integrated Circuit for the Parallel Updating Chaotic Tabu Search Hardware System |
| Sub Title (in English) | |
| Keyword(1) | combinatorial optimization problem |
| Keyword(2) | quadratic assignment problem |
| Keyword(3) | chaotic taboo search |
| Keyword(4) | chaotic neural network |
| 1st Author's Name | Akihito TOYODA |
| 1st Author's Affiliation | Graduate School of Engineering, Tokyo Denki University() |
| 2nd Author's Name | SYU Tanaka |
| 2nd Author's Affiliation | Graduate School of Engineering, Tokyo Denki University |
| 3rd Author's Name | Yosihiko HORIO |
| 3rd Author's Affiliation | Graduate School of Engineering, Tokyo Denki University |
| 4th Author's Name | Kazuyuki AIHARA |
| 4th Author's Affiliation | Institute of Industrial Science, The University of Tokyo |
| Date | 2014-01-21 |
| Paper # | NLP2013-140 |
| Volume (vol) | vol.113 |
| Number (no) | 383 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |